Exploiting All-Programmable System on Chips for Closed-Loop Real-Time Neural Interfaces

High-density microelectrode arrays (HDMEAs) feature thousands of recording electrodes in a single chip with an area of few square millimeters. The obtained electrode density is comparable and even higher than the typical density of neuronal cells in cortical cultures. Commercially available HDMEA-based acquisition systems are able to record the neural activity from the whole array at the same time with submillisecond resolution. These devices are a very promising tool and are increasingly used in neuroscience to tackle fundamental questions regarding the complex dynamics of neural networks. Even if electrical or optical stimulation is generally an available feature of such systems, they lack the capability of creating a closed-loop between the biological neural activity and the artificial system. Stimuli are usually sent in an open-loop manner, thus violating the inherent working basis of neural circuits that in nature are constantly reacting to the external environment. This forbids to unravel the real mechanisms behind the behavior of neural networks. The primary objective of this PhD work is to overcome such limitation by creating a fullyreconfigurable processing system capable of providing real-time feedback to the ongoing neural activity recorded with HDMEA platforms. The potentiality of modern heterogeneous FPGAs has been exploited to realize the system. In particular, the Xilinx Zynq All Programmable System on Chip (APSoC) has been used. The device features reconfigurable logic, specialized hardwired blocks, and a dual-core ARM-based processor; the synergy of these components allows to achieve high elaboration performances while maintaining a high level of flexibility and adaptivity. The developed system has been embedded in an acquisition and stimulation setup featuring the following platforms: \u2022 3\ub7Brain BioCam X, a state-of-the-art HDMEA-based acquisition platform capable of recording in parallel from 4096 electrodes at 18 kHz per electrode. \u2022 PlexStim\u2122 Electrical Stimulator System, able to generate electrical stimuli with custom waveforms to 16 different output channels. \u2022 Texas Instruments DLP\uae LightCrafter\u2122 Evaluation Module, capable of projecting 608x684 pixels images with a refresh rate of 60 Hz; it holds the function of optical stimulation. All the features of the system, such as band-pass filtering and spike detection of all the recorded channels, have been validated by means of ex vivo experiments. Very low-latency has been achieved while processing the whole input data stream in real-time. In the case of electrical stimulation the total latency is below 2 ms; when optical stimuli are needed, instead, the total latency is a little higher, being 21 ms in the worst case. The final setup is ready to be used to infer cellular properties by means of closed-loop experiments. As a proof of this concept, it has been successfully used for the clustering and classification of retinal ganglion cells (RGCs) in mice retina. For this experiment, the light-evoked spikes from thousands of RGCs have been correctly recorded and analyzed in real-time. Around 90% of the total clusters have been classified as ON- or OFF-type cells. In addition to the closed-loop system, a denoising prototype has been developed. The main idea is to exploit oversampling techniques to reduce the thermal noise recorded by HDMEAbased acquisition systems. The prototype is capable of processing in real-time all the input signals from the BioCam X, and it is currently being tested to evaluate the performance in terms of signal-to-noise-ratio improvement

Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays

Microelectrode array (MEA) systems with up to several thousands of recording electrodes and electrical or optical stimulation capabilities are commercially available or described in the literature. By exploiting their submillisecond and micrometric temporal and spatial resolutions to record bioelectrical signals, such emerging MEA systems are increasingly used in neuroscience to study the complex dynamics of neuronal networks and brain circuits. However, they typically lack the capability of implementing real-time feedback between the detection of neuronal spiking events and stimulation, thus restricting large-scale neural interfacing to open-loop conditions. In order to exploit the potential of such large-scale recording systems and stimulation, we designed and validated a fully reconfigurable FPGA-based processing system for closed-loop multichannel control. By adopting a Xilinx Zynq - all-programmable system on chip that integrates reconfigurable logic and a dual-core ARM-based processor on the same device, the proposed platform permits low-latency preprocessing (filtering and detection) of spikes acquired simultaneously from several thousands of electrode sites. To demonstrate the proposed platform, we tested its performances through ex vivo experiments on the mice retina using a state-of-the-art planar high-density MEA that samples 4096 electrodes at 18 kHz and record light-evoked spikes from several thousands of retinal ganglion cells simultaneously. Results demonstrate that the platform is able to provide a total latency from whole-array data acquisition to stimulus generation below 2 ms. This opens the opportunity to design closed-loop experiments on neural systems and biomedical applications using emerging generations of planar or implantable large-scale MEA systems

On-the-fly adaptivity for process networks over shared-memory platforms

Modern MPSoC architectures incorporate tens of processing elements on a single die. This trend poses the need of expressing the parallelism of the applications in order to effectively exploit the available resources. Several models of computation have been proposed, that specify an application as a network of independent computational elements. Such models represent a suitable solution for systematic mapping of parallel applications onto multiprocessor architectures. However, the workload of a given application can abruptly vary, as well as the amount of computing resources available, depending on the overall workload of the system and on the input data dependency. Traditional worst-case designs may overestimate workloads, leading to resource wasting and unnecessary power consumption. To overcome such limitation, in this work we devise a fast, run-time and automatic approach able to quickly re-configure the core-to-task mapping and the degree of parallelism of the application when the available resources or the application workload change, targeting shared-memory platforms. Experiments, carried out using an FPGA implementation, demonstrate the effectiveness of the proposed approach, in terms of achievable speed-up, power saving and introduced overhead

On-the-fly adaptivity for process networks over shared-memory platforms

Modern MPSoC architectures incorporate tens of processing elements on a single die. This trend poses the need of expressing the parallelism of the applications in order to effectively exploit the available resources. Several models of computation have been proposed, that specify an application as a network of independent computational elements. Such models represent a suitable solution for systematic mapping of parallel applications onto multiprocessor architectures. However, the workload of a given application can abruptly vary, as well as the amount of computing resources available, depending on the overall workload of the system and on the input data dependency. Traditional worst-case designs may overestimate workloads, leading to resource wasting and unnecessary power consumption. To overcome such limitation, in this work we devise a fast, run-time and automatic approach able to quickly re-configure the core-to-task mapping and the degree of parallelism of the application when the available resources or the application workload change, targeting shared-memory platforms. Experiments, carried out using an FPGA implementation, demonstrate the effectiveness of the proposed approach, in terms of achievable speed-up, power saving and introduced overhead

A closed-loop system for neural networks analysis through high density MEAs

In this work we present a FPGA-based system for real-time processing of neural signals acquired by commercial high-density microelectrode array (HDMEA). The considered MEA features 4096 electrodes with 18kHz sampling frequency and 12-bit resolution, thus produces nearly 1 Gbps of data. Within the implementation, we considered low-latency as a main objective, to allow for closed-loop acquisition-stimulation experiments, that represent a novel promising frontier in neuro-physiology and in the development of brain-machine interfaces. The developed platform is implemented on a low-to-mid Zynq all-programmable SoC, and is able to perform all the required computation (from signal acquisition to response generation) with less than 2ms latency, enabling closed-loop applications in a wide range of experiments

On-FPGA real-time processing of biological signals from high-density MEAs: A design space exploration

High-density microelectrode arrays (HDMEAs) are promising tools to tackle fundamental questions in neuroscience and brain diseases with unprecedented experimental capabilities. The acquisition of the biological signals sampled by such MEAs, that usually involves filtering, preliminary processing and finally data storage, is an intrinsically parallel and computation-intensive activity, particularly in systems targeting thousands of recording channels acquired with sub-millisecond time resolution. Within several applications, these operations need to be performed in real-time. A promising solution offering an adequate performance level relies on parallel hardware structures, making FPGA devices the perfect target technology.\\In this paper, we present an evaluation of an acquisition and processing system, to be implemented on an FPGA device, which is conceived to be connected to multi-channel CMOS-MEAs and is specifically designed for in-vitro and in-vivo recordings of neural activity. The template, implemented on reconfigurable logic, performs the first steps of the computing chain: filtering and adaptive detection of neural spikes. The filtered samples together with information regarding the presence of spikes are stored in an external DDR memory, for further elaboration and communication with the external environment. We performed a design space exploration measuring resource utilization and precision of the detection algorithm for different use-cases, corresponding to different state-of-the-art HDMEAs, and for different application parameters, such as the filtering scheme, number of parallel input channels, and sampling frequency. A prototype instance of the proposed platform, implemented on a low-end Xilinx Zynq SoC, allows to process more than 1 Gbps of data coming from up to 4096 18-kHz channels, within a time latency of 1.8 ms